1. Field of the Invention
The present invention relates to semiconductor memory devices and particularly to configurations of multiport static random access memories (hereinafter referred to as multiport SRAMs).
2. Description of the Background Art
FIG. 14 is a circuit diagram of a configuration in a first example of a memory cell used for a conventional 2-port static random access memory (SRAM), as described for example in Japanese Patent Laying-Open No. 1-251384. This memory cell will hereinafter be referred to as a 2-port SRAM memory cell.
As shown in FIG. 14, a 2-port SRAM memory cell M100 includes a latch circuit having p and n MOS transistors P100 and N100 connected in series between a power supply potential Vcc and a ground potential GND, and p and n MOS transistors P101 and N101 connected in series between power supply potential Vcc and ground potential GND.
MOS transistors P100, N100 have their respective gates both connected to a node S101 connecting MOS transistors P101 and N101. (Hereinafter this node will also be referred to as storage node S101.) MOS transistors P101, N101 have their respective gates both connected to a node connecting MOS transistors P100 and N100. (Hereinafter this node will also be referred to as a storage node S100.) In other words, p MOS transistors P100, P101 operate as load transistors and n MOS transistors N100, N101 operate as drive transistors.
2-port SRAM memory cell M100 further includes n MOS transistors N102, N103 connected between complementary write bit lines WB and /WB and storage nodes S100, S101, respectively. MOS transistors N102, N103 have their respective gates both connected to a common word line WWL. As such, MOS transistors N102, N103 have their respective gate potentials controlled via write word line WWL.
2-port SRAM memory cell M100 further includes n MOS transistors N104, N105 connected between complementary read bit lines RB and /RB and storage nodes S100, S101, respectively. MOS transistors N104, N105 have their respective gates both connected to a common read word line RWL. As such, MOS transistors N104, N105 have their respective gate potentials controlled via read word line RWL.
Thus p MOS transistors P100, P101 serve as load transistors and n MOS transistors N100, N101 serve as drive transistors, and n MOS transistors N102–N105 serve as access transistors to implement a so-called “CMOS” 2-port SRAM memory cell.
More specifically in the FIG. 14 2-port SRAM memory cell M100 while write word line WWL is active (or has the high level (or a power supply potential level)) data is written to storage nodes S100 and S101 via complementary write bit lines WB, /WB, respectively. While write word line WWL is inactive (or has the low level (or a ground potential level)) the data once written to storage nodes S100 and S101 is held steadily by a latch circuit formed of MOS transistors P100, P101, N100, N101.
While read word line RWL is active, data is read from storage nodes S100, S101 via complementary bit lines RB, /RB.
It is not necessary to periodically turn on word line WWL to effect refresh operation and data can be held in standby state in a memory cell. Hereinafter p MOS transistors P100, P101 will also be referred to as load transistors P100, P101, and n MOS transistors N100, N101 as drive transistors N100, N101, and n MOS transistors N102–N105 as access transistors N102–N105.
For the CMOS, 2-port SRAM memory cell, there have also be proposed other than the above first example of configuration a large number of examples in configuration that allow for rapid-reading and reduction in voltage, as disclosed for example in U.S. Pat. No. 6,201,758 and Japanese Patent Laying-Open No. 2001-143473.
The 2-port SRAM memory cell having a second exemplary configuration (not shown) has, as well as FIG. 14, series-connected p and n MOS transistors forming pair of inverters cross coupled to form a latch circuit to provide a CMOS configuration, and between a first read bit line and a first storage node a first n MOS transistor is arranged and between a second read bit line complementary to the first read bit line and a second storage node a second n MOS transistor is connected. The first and second n MOS transistors have their respective gate potentials both controlled via a read word line.
Between the first storage node and a ground potential, series connected, third and fourth n MOS transistors are connected. Between the second storage node and a ground potential, series-connected, fifth and sixth n MOS transistors are connected. The third and fifth n MOS transistors have their respective gate potentials controlled via a write word line. The fourth and sixth n MOS transistors have their respective gates connected to complementary first and second write bit lines, respectively.
Generally in an SRAM memory cell if a ratio in current driving force between an access transistor and a drive transistor that stores data is reduced then when a bit line is connected a storage node having the low level tends to readily increase in potential and static noise margin is reduced and accordingly data is held less steadily. In other words, the data held in the memory cell is destroyed and as a result an erroneous operation is caused. This ratio is generally referred to as β ratio and typically to ensure static noise margin the ratio is set to approximately three to four. In other words, a drive transistor is required to have a current driving force set to be higher than an access transistor.
The FIG. 14 conventional, 2-port SRAM memory cell M100 current driving force ratio (β ratio) will now be studied. Note that hereinafter drive transistor N100 will have a current driving force represented as DN100, access transistors N102, N104 will have those represented as DN102, DN104. Furthermore, current driving forces DN102, DN104 are set equivalently for the sake of illustration.
In 2-port SRAM memory cell M100 if data are written and read to and from memory cells of a single row, as differently timed, then, in response to write word line WWL and read word line RWL being activated, access transistors N102, N103 and access transistors N104, N105 are turned on as differently timed. As such, the β ratio is equal to that for a single-port SRAM, provided by DN100/DN102.
By contrast, if data are written and read to and from memory cells of a single row, as identically timed, access transistors. N102, N103 and access transistors N104, N105 are turned on as identically timed. The β ratio will be DN100/DN102×2, which is half that for a single-port SRAM and data would be held less steadily.
Thus in 2-port SRAM memory cell M100 two types of β ratio depending on patterns of the number of access transistors turned on are introduced and to ensure that data is held steadily the β ratios are both required to hold the level of the β ratio for single-port SRAM. In particular, multiport SRAMs have further increased patterns in number of access transistors turned on, and β ratio must be considered for each pattern.
Accordingly to ensure that a multiport SRAM holds data steadily a drive transistor's current driving force may advisably be set high. If the current driving force is set to high, however, the latch circuit enters an excessively stable state, which can render it difficult to write data.
Furthermore in recent years semiconductor integrated circuits are required to operate on reduced power supply voltages. This results in an SRAM memory cell holding data less steadily. Thus for multiport SRAMs it is increasingly difficult to ensure that data is held steadily and also ensure sufficient write margin.
Furthermore the above described, conventional multiport SRAM memory cell, in any configuration, has each port corresponding to only one of reading and writing data and does not allow a single port to accommodate both reading and writing data. This is an obstacle to freely designing a circuit.